A common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is a storage element, such as a register. Often so called edge triggered registers (“flip flops”) are used. In these circuits, pairs of latch elements are serially coupled back to back and are clocked by a constant duty cycle clock. The front latch is opened on a rising pulse of the clock signal, while the second latch, which provides the output signal, is opened during a rising edge of an inverted clock signal. The result is that the edge triggered flip flop has a stable output for the majority of each clock cycle, making use of the outputs in combinatorial logic between clocked registers fairly easy as the critical path in logical circuitry can reliably use the “Q” or inverted “Q” or “Q_” outputs for most of the clock cycle without any timing problems.
However, these edge triggered flip flop registers require several transistors, consume significant silicon area, and consume significant power. The power consumption problem is further increased by the consumption of power even when the input to the stage has not changed, for example when the register is not in active use by the system. Each time a clock edge arrives, transistors in the circuit change state and thus use power—even for cycles where the input is stable and/or the output is not being used.
Various approaches to reducing the power consumption in integrated circuits have been proposed. Clock gating approaches provide a clock signal to portions of an integrated circuit (or other circuitry, for that matter) which is not allowed to transition when the circuit is not in use. The clock is then gated by an enable signal. This approach can save power but adds additional logic circuitry, control circuitry, and signal routing requirements to form and route the gated clock signals to the registers in place of the clock signals.
Another approach is to form power gating circuitry. Power gating circuitry includes logic and control circuitry to remove the power signals to portions of the integrated circuit, and in particular to registered elements when they are not in use. Again, this approach requires additional logic and control circuitry and routing various signals to portions of the integrated circuit. One advantage that power gating achieves over clock gating is that it conserves both dynamic power (power consumed due to clock switching) and standby or static power (power consumed to maintain state of the registers in the absence of clock switching).
Some other known approaches use frequency compensation to reduce dynamic power consumption. In this approach, the clock signals are reduced in frequency when possible to reduce the number of switching cycles over a time interval and thereby reduce the consumption of dynamic power. Again, additional control and logic circuitry are needed.
In some circuits, some reduction in power consumption is possible by reducing the voltage level of the positive supply slightly to portions of a circuit; however, this approach also requires added circuitry and added routing channels, and reduces the signal margins of the circuit, which can impose additional constraints or risks on the design process.
Recently, the attempt to reduce power consumption has resulted in the use of “pulsed latch” circuits instead of register circuits for storage. In this approach, a latch circuit, which has approximately half of the transistors and silicon area requirements of a registered flip flop, is used with a pulsed clock to open the latch and close it. By reducing the duty cycle of the pulsed clock, the input is sampled for a portion of the clock cycle, but then the latch closes and the output remains constant for the remainder of the clock cycle. In a paper presented by Tschanz, et al. in 2001 entitled “Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High Performance Microprocessors”, power usage and delay characteristics were compared for several differing pulsed clock latches and flip-flops. In applications where power savings is the primary concern, one particular pulsed latch circuit, which in the paper is referred to as “explicit pulsed hybrid static flip-flop” or EP-SFF was shown to be superior. In addition, it is possible for the pulsed clock signal to be shared among several of these pulsed latch circuits and additional power and area savings can therefore be achieved.
FIG. 1 depicts a simple circuit diagram of a prior art pulsed latch circuit such as referred to in the Tschanz reference. In FIG. 1, an input transmission gate comprised of transistors MN1 and MP1 samples or receives a data input when the pulsed clock signal “PCLK” is active. Inverters I5 and I6 form a recirculating latch, which will recirculate the data in the latch unless that data is overwritten by new incoming data, as is known in the art. Output driver inverter OUTB will then provide the output Q_.
Inverter I4 provides PCLK from the output of NAND GATE N1. Inverters I1, I2, I3 and NAND gate N1 form a clock pulse generator circuit that, at a falling edge of the clock signal CLK, will generate a “zero” pulse on PCLK_ that is only the width of the delay provided by the inverting delay chain of inverters I1 and I2, I3. Thus, by increasing or decreasing the length of the delay line, the pulse width may be varied but is fixed at a designed delay time. Variations in the device performance caused by, for example, operating temperature or process variation effects, will change the delay obtained and thus the pulse clock PCLK_ operation.
If the high portion of the pulse on pulsed clock signals PCLK/PCLK is too long, then the latch may capture data too early and cause a “flash through” timing problem, that is, in a counter or shift register circuit the pulse latch register may skip a clock cycle, resulting in erroneous operation. On the other hand, if the pulse becomes too short, the register may not have the input gates MN1 and MP1 open for a time long enough to change the internal stored value, thus the input data could be missed and not captured.
FIGS. 2(a), 2(b) and 2(c) depict in three schematic views variations on the prior art pulsed clock circuit that are used. All of these circuits will output a pulsed clock from a time varying clock signal input. Typically, the time varying clock has a 50% duty cycle and the pulsed clock signal has a duty cycle of 10-30%, that is, the high part of the pulsed clock duty cycle is shorter than the rest. In FIG. 2(a), the circuit used in the prior art pulse latch of FIG. 1 is depicted. FIG. 2(b) illustrates an alternative circuit arrangement that uses additional pull up and pull down devices MP1 and MN1 to improve the performance. FIG. 2(c) depicts an alternative arrangement similar to FIG. 2(c) but incorporating a scan path input SE for clocking the pulsed latch during test or other scan operations as is known in the art.
The prior art pulse clock generators of FIG. 2 may be designed for different delay lengths by changing the devices used such as MP1 and MN1 or the number and size of the inverters used, however, after the integrated circuit device containing the pulsed latch is completed, temperature dependent or process dependent effects may undesirably change the pulse width obtained on the pulsed clock output. This change in pulse width may negatively affect the operation of the circuits and/or the yield of a fabrication facility.
Thus, there is a continuing need for a pulsed clock circuit and methods that provide a pulsed clock signal for use with pulsed latch circuitry. The pulsed clock signal has a desired pulse width that is maintained more or less constant, in spite of variations in temperature and process related circuit variations, is adapted to changes in conditions, and the circuit and methods should remain compatible with existing and future semiconductor processes for fabricating integrated circuits.